The hallmark of progress in semiconductor integrated circuit technology in the past decade has been improvements in such integrated circuit features as density, speed and performance. This has been made possible, in part, due to improvements in semiconductor processing techniques such as new lithography (optical and non-optical) methods capable of submicrometer exposures, replacement of wet etching by dry methods--plasma etching, reactive ion etching (RIE) and ion beam milling--to bypass the deficiencies of wet etching, use of low resistivity silicides and refractory metals as replacements for high-resistivity polysilicon interconnections and multiple photoresists to compensate for wafer surface variations that thwart accurate fine-line lithography.
The main driving force behind this progress has been the advantages of scaling, i.e. reducing, the device dimensions since scaling is directly linked to reduced fabrication cost and improved performance. Scaling down boosts circuit density by the square of the scale factor (which is defined as the ratio of the original dimension to the reduced dimension). The end result of this is more elements per chip area and more devices per wafer, the latter cutting the cost of manufacture. Scaling also reduces a circuit's operating power, capacitance, and delay times since these parameters are dependent on the dimensions of the circuit.
Despite this impressive progress, the prior art imposes an inherent limitation on device density due to the requirement that the various active and passive devices of the integrated circuit be dielectrically isolated from one another and such isolation consumes valuable chip real estate. To elaborate on this, reference is made to two most commonly used dielectric isolation schemes, the recessed oxide isolation (ROI) and the polyimide- or polysilicon-filled trench isolation (PIT). FIG. 1 shows a prior art widely used ROI for a vertical NPN bipolar device and can be better understood by reference to the Peltzer U.S. Pat. No. 3,648,125 and I. Magdo, et al. patent application Ser. No. 150,609, filed June 7, 1971. In FIG. 1 the base region 12 contains the emitter region 14. A N+ reach-through region 16 contacts the N+ subcollector region 18 which is located on the P- substrate 10. The base, emitter and collector contact electrodes are designated, respectively, by B, E and C. The ROI regions 20 dielectrically isolate surface regions of substrate 10 containing the bipolar transistors. Provided underneath each ROI region 20 is a P+ isolation region 22 to prevent an electrical short between N+ regions 18 of one transistor and the next caused by the downward segregation, during the thermal growth of the ROI regions, of the N-type epitaxial regions directly underneath the ROI regions 20. However, since the region 22 has a high concentration of P-type dopant, it needs to be spaced from the subcollector regions 18 having a high concentration of N-type dopant, otherwise the PN junctions formed between the regions 18 and 22 may cause dislocations leading to leakage of the bipolar devices. Also, since the regions 22 is relatively deep and encircles the subcollector 18, the junction capacitance between these regions tends to build up to a high level rendering the transistor slow.
Typically, the width of the P+ isolation region 22 is about 2.5 .mu.m. The spacing between the subcollector 18 and the isolation region 22 is dictated by the particular application of the transistor. For example, for memory application this spacing is about 2 .mu.m and for high speed logic applications it is about 5 .mu.m. In other words, a prior art transistor which is dielectrically isolated by ROI requires a collector-to-collector spacing of about 6.5 .mu.m or 12.5 .mu.m depending on whether it is intended for memory or high speed logic applications, respectively.
To overcome the above problems associated with ROI, trench isolation, shown in FIG. 2, has been devised. This prior art dielectric isolation can be better understood by reference to the Pogge U.S. Pat. No. 4,104,090 and Bondur et al. U.S. Pat. No. 4,104,086 both assigned to the assignee of the present application. In FIG. 2 the various elements designated by primed numbers correspond to their counterpart elements in FIG. 1 designated by numbers without the prime. In the trench isolation scheme, the ROI 20 of FIG. 1 is substituted with a rather deep polysilicon- or polyimide-filled trench 20'. Since the P+ isolation 22' is spaced sufficiently far away from the N+ subcollector 18', the problem of a high junction capacitance between these highly doped regions, which exists in the ROI scheme, is absent in trench isolation. Another advantage of the trench isolation is that the width of the trench, regardless of whether it is filled with polysilicon or polyimide and regardless of whether the transistor is intended for memory or high speed logic applications, is small (typically 1.5 .mu.m) compared with that of the ROI.
However, trench isolation requires a complex series of process steps to insure against troublesome creepage of dislocations or injection of charges from the sides of the trench thereby rendering the trench ineffective. Also, despite the significantly reduced width of the trench isolation compared to that of ROI, to fabricate very high density and performance circuits of the future the demands placed on the chip real estate by this isolation scheme is still rather high.
In addition to the stringent demands placed on the valuable chip real estate by the prior art isolation schemes, the prior art bipolar devices require all contacts to the various elements of the device be made on the top surface of the monolithic silicon. Since the contacts are photolithographically defined, the silicon real estate occupied by these contacts cannot be reduced beyond a certain limit. To elaborate on this, reference is made to FIG. 3 which is a top view of the bipolar device illustrated in FIGS. 1 and 2 without the encircling dielectric isolation. As illustrated in FIG. 3, the contacts B, C and E require an approximately common width W2 and lengths L2, L4 and L6, respectively. Also, the contacts need to be spaced from each other or the dielectric isolation by the indicated spacings of L1, L3, L5, L7, W1 or W3. Consequently, silicon area occupied by the transistor has a dimension in one direction of L1+L2+L3+L4+L5+L6+L7 and a dimension in the perpendicular direction of W1+W2+W3. Even if it were possible to reduce these dimensions to the smallest spacing A that can be achieved by conventional photolithography, the area occupied by the transistor will be as much as 7A.times.3A. In other words, any area reduction that can be attained in the prior art transistors is constrained by the lithography limits.
Accordingly, it is an object of the invention to provide an integrated circuit having an increased device density, by reducing the silicon area occupied by the device structures.
It is another object of the invention to provide integrated circuit devices having an improved performance resulting from reduction in the device size and associated parasitic capacitances.
It is another object of the invention to eliminate the dielectric isolation between one integrated circuit device and the next.
Another object of the invention is to provide a process of forming the above integrated circuit by means of a significantly reduced number of masking steps compared to the prior art processes.